High Performance Reduced Instruction Set Processors

The focus of this paper is on high performance. In general purpose computing environments, a very large fraction of instructions executed are simple: load, store, add, shift, compare, logic, and branch. To obtain high speeds, sequences of simple instructions must be executed as fast as possible. This paper describes compiler, architecture, and machine organization approaches that result in efficient use of hardware and very high execution speeds. We show how pipeline disruptions can be (almost) eliminated by proper architecture design and appropriate compiler optimizations. The penalties due to cache misses can be significant , and approaches to reducing these penalties are presented. We describe a series of techniques and show the effect of each one on performance.

We do not recommend a pure RISC approach for all applications and environments. If complex operations (such as floating point arithmetic) are important, direct hardware implementation of the functions my be necessary to meet performance targets. Even in these cases, however, it is possible to extend the basic RISC approach and expose the hardware to the compiler to obtain better efficiencies. High speed execution of three important complex operations including movement of character strings in memory and floating point arithmetic will be presented in this paper.